Plasma display panels (hereinafter, referred to as “PDPs”) are a type of flat panel displays (FPDs) capable of high-speed display and suitable for upsizing. Because of these advantages, PDPs are widely in practical use in many fields including the field of video display devices and public information display devices.
FIG. 10 is an assembly drawing of a general AC-driven surface discharge PDP and schematically shows the structure of discharge cells, which are the units for causing discharge. A PDP 1x shown in FIG. 10 is composed of a front panel 2 and a back panel 9 assembled together. The front panel 2 includes a glass substrate 3, a plurality of display electrode pairs 6 (each pair is made up of a scan electrode 5 and a sustain electrode 4) that are disposed on one main surface of the glass substrate 3, a dielectric layer 7 and a protective layer 8 that are laid in the stated order to cover the display electrode pairs 6. Each scan electrode 5 (sustain electrode 4) is composed of a transparent electrode 51 (41) and a bus line 52 (42).
The dielectric layer 7 is made of low-melting glass having a softening point temperature on the order of 550° C. to 600° C. The dielectric layer 7 performs a current limiting function that is specific to an AC-PDP.
The protective layer 8 is made of magnesium oxide (MgO), for example. The protective layer 8 protects the dielectric layer 7 as well as the display electrode pairs 6 from ion bombardment at the time of plasma discharge. In addition, the protective layer 8 effectively emits secondary electrons thereby to reduce the firing voltage. Normally, the protective layer 8 is manufactured by vacuum vapor deposition (Patent Documents 7 and 8) or printing (Patent Document 9).
The back panel 9, on the other hand, includes a glass substrate 10 and a plurality of data (address) electrodes 11 disposed on a main surface of the glass substrate 10. The plurality of data electrodes 11 are used to address image data and disposed in parallel to one another and extend in a direction orthogonal to the display electrode pairs 6 disposed on the front panel 2. The back panel 9 additionally includes a dielectric layer 12 made of low-melting glass and laid to cover the data electrodes 11 and the glass substrate 10 at least partially. In addition, barrier ribs 13 made of low-melting glass are disposed on the dielectric layer 12 to partition a discharge space 15 into a plurality of discharge cells (not illustrated). More specifically, the barrier ribs 13 are of a predetermined height and composed of portions 1231 and 1232 coupled to form a grid pattern at locations coinciding with boundaries between the adjacent discharge cells. Phosphor layers 14 of the respective colors of R, G, and B (phosphor layers 14R, 14G, and 14B) are formed one each between each two adjacent barrier ribs 13, by applying and burning phosphor inks of the respective colors. Each phosphor layer 14 is so disposed to cover the side surfaces of the adjacent barrier ribs 13 and the surface of the dielectric layer 12 exposed between the barrier ribs 13.
The front and back panels 2 and 9 are placed relatively to each other in a parallel spaced arrangement, such that the display electrode pairs 6 are orthogonal to the data electrodes 11. While this positional relationship is retained, the panels 2 and 9 are sealed together around their edges. The space enclosed therein is filled with a rare gas as a discharge gas, at a pressure of about several tens of kilopascals. Examples of the rare gas include a rare gas mixture such as xenon-neon or xenon-helium. This concludes the description of how the PDP 1x is structured.
It is generally noted that the discharge characteristics of a PDP largely depend on the property of a protective layer provided. Various studies have been made in order to improve the discharge characteristics. One of the problems receiving the greatest attention is a problem of discharge delay.
The term “discharge delay” refers to a phenomenon in which discharge occurs with a delay from the leading edge of a pulse when a PDP is driven at high speed by applying narrow pulses. As the discharge delay increases, there is a smaller chance that the discharge completes within the duration corresponding to the pulse width. In such a case, some of the discharge cells may not be addressed as intended, which results in lighting failure.
Several attempts have been made to solve the problem of discharge delay. In one attempt, MgO is doped with such elements as Fe, Cr, and V or alternatively added with Si and Al. By the presence of those dopants, the discharge characteristics of the protective layer improve (Patent Documents 1, 2, 4, and 5). In another attempt, an MgO film is formed directly on a dielectric layer or by a thin-film method, and single-crystal particles containing MgO particles formed by a vapor-phase oxidation process are disposed in a layer on the MgO thin-film. With this arrangement, the discharge characteristics of the protective layer surface improves (Patent Document 3). The latter attempt is said to provide a certain level of improvement on the discharge delay at low temperatures.
Patent Document 1: JP Patent Application Publication No. 08-236028;
Patent Document 2: JP Patent Application Publication No. 10-334809;
Patent Document 3: JP Patent Application Publication No. 2006-054158;
Patent Document 4: JP Patent Application Publication No. 2004-134407;
Patent Document 5: JP Patent Application Publication No. 2004-273452;
Patent Document 6: JP Patent Application Publication No. 2006-147417;
Patent Document 7: JP Patent Application Publication No. 05-234519;
Patent Document 8: JP Patent Application Publication No. 08-287833;
Patent Document 9: JP Patent Application Publication No. 07-296718;
Patent Document 10: JP Patent Application Publication No. 10-125237
Non-Patent Document 1: Chem. Phys. Vol. 90, No. 2, 807, by J. F. Boas, J. (1988).